***************** PCI Configuration Registers ****************** 00: 0x1004 Vendor ID (0x1004) 02: 0x0702 Device ID (0x0702) 04: 0x0146 Command (default: 0x0004) Enable response in Memory space Enable bus mastering Enable parity checking Enable system error 06: 0x2280 Status (default: 0x0680) Accept fast-back to back DEVSEL timing: Medium Master abort 08: 0x06000011 Class / Revision Class: 0x060000 (0x060000) Revision: VAS96011-P2 0c: 0x08 Cache Line Size (default: 0x08) 32 bytes 0d: 0x00 Latency Timer (default: 0x00) 0e: 0x00 Header Type (0x00) 0f: 0x00 BIST (0x00) 10: 0x00000000 Base Address 0 (0x00000000) 14: 0x00000000 Base Address 1 (0x00000000) 18: 0x00000000 Base Address 2 (0x00000000) 1c: 0x00000000 Base Address 3 (0x00000000) 20: 0x00000000 Base Address 4 (0x00000000) 24: 0x00000000 Base Address 5 (0x00000000) 28: 0x00000000 Cardbus CIS (0x00000000) 2e: 0x0000 Subsystem ID (0x0000) 2c: 0x0000 Subsystem Vendor ID (0x0000) 30: 0x00000000 ROM Address (0x00000000) 34: 0x00000000 (0x00000000) 38: 0x00000000 (0x00000000) 3c: 0x00 Interrupt Line (0x00) 3d: 0x00 Interrupt Pin (0x00) 3e: 0x00 Minimum Grant (0x00) 3f: 0x00 Maximum Latency (0x00) 40: 0x00 Bus Number (default: 0x00) 41: 0x00 Subordinate Bus Number (default: 0x00) 42: 0x00 Disconnect Counter (0x00) 43: 0x00 (0x00) 44: 0x00000000 (0x00000000) 48: 0x00000000 (0x00000000) 4c: 0x00000000 (0x00000000) ***************** PowerPC Interface Registers ****************** 50: 0x0bfe0009 PPC Interface Control Snoop Type: Address-only Timeout Count: 511 Endianness: Big Allowed CPU cycles while pending PCI-to-memory cycle: Disabled Fast L2 and NO DRTRY: Enabled Arbiter Pipeline: Disabled Internal Arbiter: Enabled 54: 0x00000000 (0x00000000) 58: 0x00000000 (0x00000000) ********************* Address Map Register ********************* 5c: 0x00000010 Address Map Top of emulated memory: 0x000 MB CHRP PC emulation: Disabled PReP ISA master fix: Disabled Discontiguous ISA I/O: Disabled CHRP system memory alias and peripheral memory alias options: Enabled CHRP processor hole: Disabled CHRP I/O hole: Disabled Address map: CHRP ******************* PCI Interface Registers ******************** 60: 0x40012c00 PCI Interface Control PCI clock: Sychronous Frame buffer size: 1 MB Frame buffer base: +0x000 MB Frame buffer byte-merging: Disabled Word-combining: Enabled PCI transaction snooping: Enabled Prefetch from PCI slaves in frame buffer range: Disabled Prefetch from PCI memory: Enabled Timeout for first data-beat: 32 PCI clocks PCI Bus Read streaming from memory: Disabled Number of retries before target abort: 255 64: 0x00000000 (0x00000000) 68: 0x00000000 (0x00000000) 6c: 0x00000000 (0x00000000) ******************* ROM Controller Registers ******************* 70: 0x00000011 ROM Interface Control ROM bank 1 shadow size: 0x400 KB ROM shadow base address: 0x00000000 ROM bank 0 shadow size: 0x1000 KB ROM bank 1 width: 16 bit Flash ROM bank 1 write: Disabled ROM bank 0 operating mode: Disabled ROM bank 0 width: 64 bit Flash ROM bank 0 write: Disabled ROM bank 0 operating mode: Enabled 74: 0x0ffe0552 ROM Timing ROM bank 1 access time for 2nd to last data beat: 18 clocks ROM bank 1 access time for first data beat: 21 clocks ROM bank 1 off time: 9 clocks ROM bank 0 access time for 2nd to last data beat: 8 clocks ROM bank 0 access time for first data beat: 11 clocks ROM bank 0 off time: 3 clocks 78: 0x00000000 (0x00000000) 7c: 0x00000000 (0x00000000) ****************** Cache Controller Registers ****************** 80: 0x03ff8e8d Cache Controller Control Tag pattern for invalid lines: 0x3ff ROM caching: Enabled Write-back policy for dirty write misses: Deferred Write-back policy for dirty read misses: Deferred Tag mask: 512K/10 bit tag Cache size: 512 KB Tag SRAM access time: < 15 s Data SRAM type: Pipelined Synchronous Cache mode: Write-thru 84: 0x00000000 (0x00000000) 88: 0x00000000 (0x00000000) 8c: 0x00000000 (0x00000000) ****************** DRAM Controller Registers ******************* 90: 0x00001c05 DRAM Bank #0 Control DRAM bank #0 base address: 0x00000000 DRAM bank #0 timing set: 0 DRAM bank #0 size: 16 MB DRAM bank #0 chip geometry: 9R x 9C DRAM bank #0 chip type (don't care if SDRAM controller is enabled): EDO DRAM bank #0: Enabled 94: 0x00041c05 DRAM Bank #1 Control DRAM bank #1 base address: 0x01000000 DRAM bank #1 timing set: 0 DRAM bank #1 size: 16 MB DRAM bank #1 chip geometry: 9R x 9C DRAM bank #1 chip type (don't care if SDRAM controller is enabled): EDO DRAM bank #1: Enabled 98: 0x00081c05 DRAM Bank #2 Control DRAM bank #2 base address: 0x02000000 DRAM bank #2 timing set: 0 DRAM bank #2 size: 16 MB DRAM bank #2 chip geometry: 9R x 9C DRAM bank #2 chip type (don't care if SDRAM controller is enabled): EDO DRAM bank #2: Enabled 9c: 0x000c1c05 DRAM Bank #3 Control DRAM bank #3 base address: 0x03000000 DRAM bank #3 timing set: 0 DRAM bank #3 size: 16 MB DRAM bank #3 chip geometry: 9R x 9C DRAM bank #3 chip type (don't care if SDRAM controller is enabled): EDO DRAM bank #3: Enabled a0: 0x00000000 DRAM Bank #4 Control DRAM bank #4 base address: 0x00000000 DRAM bank #4 timing set: 0 DRAM bank #4 size: 128 MB DRAM bank #4 chip geometry: 9R x 9C DRAM bank #4 chip type (don't care if SDRAM controller is enabled): Fast-page Mode DRAM bank #4: Disabled a4: 0x00000000 DRAM Bank #5 Control DRAM bank #5 base address: 0x00000000 DRAM bank #5 timing set: 0 DRAM bank #5 size: 128 MB DRAM bank #5 chip geometry: 9R x 9C DRAM bank #5 chip type (don't care if SDRAM controller is enabled): Fast-page Mode DRAM bank #5: Disabled a8: 0x00000000 (0x00000000) ac: 0x00000000 (0x00000000) b0: 0x1400001c DRAM Timing Set #0 DRAM timing RAS precharge time: 2 clocks DRAM: DRAM timing set #0 row address setup time: 1 clocks DRAM timing set #0 row address hold time: 2 clocks DRAM timing column address setup time: 2 clocks DRAM timing set #0 column address hold time: 1 clocks DRAM timing set #0 CAS precharge time: 1 clocks DRAM timing set #0 CAS pulse width: 1 clocks DRAM timing set #0 RAS pulse width: 1 clocks DRAM timing set #0 MD hold time: 1 clocks DRAM timing set #0 MD access time: 2 clocks DRAM timing set #0 CAS to RAS setup time: 1 clocks DRAM timing set #0 CAS hold time: 1 clocks DRAM timing MWE to CAS setup time: 1 clocks DRAM timing set #0 RAS kept asserted after end of transaction: Indefinite SDRAM: DRAM timing set #0 RAS to CAS delay: 2 clocks DRAM timing write recovery time: 2 clocks DRAM timing set #0 RAS pulse width: 1 clock DRAM timing set #0 RAS kept asserted after end of transaction: Indefinite b4: 0x7ffffe00 DRAM Timing Set #1 DRAM: DRAM timing set #1 row address setup time: 2 clocks DRAM timing set #1 row address hold time: 4 clocks DRAM timing set #1 column address hold time: 2 clocks DRAM timing set #1 CAS precharge time: 2 clocks DRAM timing set #1 CAS pulse width: 4 clocks DRAM timing set #1 RAS pulse width: 16 clocks DRAM timing set #1 MD hold time: 2 clocks DRAM timing set #1 MD access time: 5 clocks DRAM timing set #1 CAS to RAS setup time: 2 clocks DRAM timing set #1 CAS hold time: 2 clocks DRAM timing set #1 RAS kept asserted after end of transaction: 0 clocks SDRAM: DRAM timing set #1 RAS to CAS delay: 4 clocks DRAM timing set #1 RAS pulse width: Reserved DRAM timing set #1 RAS kept asserted after end of transaction: 0 clocks b8: 0x00000000 (0x00000000) bc: 0x00000000 (0x00000000) c0: 0x96800080 DRAM Control SDRAM controller: Enabled SDRAM controller reset: No Action SDRAM controller 2N rule: Not Enforced SDRAM controller CAS latency: 3 clocks SDRAM controller refresh cycle time: 8 clocks SDRAM early SDCKE: Disabled SDRAM clock 2: Enabled CAS lines: Gating Off (ormal) Read latch bypass for DRAM reads: Disabled DRAM refresh recovery when exiting from self-refresh: 0 cycles DRAM refresh interval between succesive refresh cycles: 512 clocks DRAM refresh staggering mode: All banks at the same time DRAM refresh type: CBR refresh DRAM parity check/generate: Parity c4: 0x00000000 (0x00000000) c8: 0x00000000 (0x00000000) cc: 0x00000000 (0x00000000) *********************** Error Registers ************************ d0: 0x910602c6 Error Control General enable for MCP interrupts: Enabled NMI forwarding: Forward PowerPC shadow overwrite: Do not notify PowerPC bus timeout error: Notify DRAM out of bounds access error for PCI masters: Notify DRAM out of bounds access error for PowerPC masters: Notify DRAM parity error: Do not notify PCI system error: Notify PCI bus retry timeout error: Notify PCI general parity error: Notify PCI master abort error: Notify PCI target abort error: Notify d4: 0x00020000 Error Status NMI flag: No Error PowerPC shadow overwrite: No Error PowerPC bus timeout error: No Error DRAM out of bounds access error for PCI masters: No Error DRAM out of bounds access error for PowerPC masters: Error DRAM parity error: No Error PCI system error: No Error PCI bus retry timeout error: No Error PCI general parity error: No Error PCI master parity error: No Error PCI target parity error: No Error PCI address parity error: No Error PCI master abort error: No Error PCI target abort error: No Error d8: 0x00000000 (0x00000000) dc: 0x00000000 (0x00000000) e8: 0x00000000 (0x00000000) ec: 0x00000000 (0x00000000) e8: 0x00000000 (0x00000000) ec: 0x00000000 (0x00000000) f8: 0x00000000 (0x00000000) fc: 0x00000000 (0x00000000) f8: 0x00000000 (0x00000000) fc: 0x00000000 (0x00000000)