The “SDRtwo” general coverage receiver described here is the result of a home building project conducted during the first half of 2006.  As the reader will appreciate, its concept is largely inspired by the series of articles "A Software-Defined Radio for the Masses” (part 1…4), by Gerald Youngblood (AC5OG) published in QEX back in 2002, my eternal gratitude to the author.

I am really fascinated by the possibilities of Software Defined Radio (SDR), especially where the computing power of the PC is used to build near ideal filters, demodulators and other signal manipulation using DSP techniques implemented in software.  The man machine interface becomes really formidable as it includes a spectrum display by which tuning to a signal becomes a child’s play as one can see it before one can hear it.  As moreover, good quality soundboards (96kS/s at 24bit) are available, the external “receiver” hardware becomes nothing more than a frequency down converter, from RF to base band.

A number of excellent freeware programs are currently available on the Internet such as PowerSDR, Rocky, M0KGK-SDR and SDRadio, coping with the SDR application on the PC. 
Some hardware (designs, kits and ready made products) is becoming available as well, the most notorious being Flexradio’s SDR-1000 and of course the Softrock-40 by Tony Parks (KB9YIG) all of them having their pros and cons.
Earlier this year I nevertheless decided to build such a receiver front end myself, this eventually became the “SDRtwo” project. 
Its design goals were as follows:
* General coverage: 0.5...30MHz
* Tuning per 1Hz
* Good sensitivity: better then 0.5µV MDS (>6 dB S/N)
* Good IP3 (due to the QSD)
* Frequency and gain controlled by the PC
* Single 9V power supply (350mA)



The SDRtwo is a quadrature direct conversion receiver front end: a set of HF pre-filters followed by a QSD and a dual low noise base band amplifier.  The quadrature local oscillator signal is generated by a DDS circuit based on the AD9854 chip fed by a 160MHz crystal oscillator. The frequency and the gain are directly controlled by a PC through its parallel port (no on board microcontroller is used).

Given the description here above, the block diagram of the front end should be easy to understand.




HF pre-selection & QSD

See part 1 for the circuit diagram.

The antenna signal is first led through a set of HF band pass filters, small relays are used to switch the signal according the received frequency. Except for the first, each filter is a 3rd order one octave band pass filter with an input/output impedance of 50Ω. The first is just 3rd order low pass filter.  The filters are implemented using conventional through hole components and moulded inductors. Care was taken to orient the inductors in right angles to minimise mutual induction.  As the QSD has high input impedance, the HF filters are not terminated (this is a bit controversial), in practise this yields an extra gain of 6dB and does not affect too much the frequency response. 

The heart of the system, the QSD detector (sometimes referred to as the D. Tayloe mixer) is implemented with the FST3253 IC.  This chip includes a dual 4:1 high speed video switch, featuring a low on resistance (4Ω per switch), a high bandwidth and above all, a high switching speed.  I will not dwell on the principle of this truly remarkable circuit, much has been published already on the Internet.  Suffice to say that it works as promised, with outstanding dynamic range and intermodulation characteristics. 
Gerald Youngblood’s design, the topology of this QSD is a bit different from most, as it is double-balanced; due to its input transformer and the arrangement of the switches each capacitor is charged twice during a single cycle.  This serves to suppress the even-order harmonic responses of the circuit, making it less sensitive to this kind of interference.
The 68nF capacitors, together with the HF source impedance of 200Ω (4:1 transformer ratio), form an RC circuit, limiting the audio bandwidth to 22kHz, which is adequate for a subsequent signal conversion at 48kHz sampling rate.

The four outputs of the QSD are fed to a set of instrumentation amplifiers build with the low noise chip INA163  (yielding 1nV/√Hz for gains of 60dB).  Their gain is set to 100 (+40dB) or to 10 (+20dB), switchable by means of a small relay.

I encountered an annoying issue associated with the QSD: charge injection of the LO into the signal path (every direct conversion receiver has this phenomenon).  The CMOS switches inside of the FST3253 may be small wonders of circuit design and technology, they still have some small capacitance between their control electrodes and the switch electrodes (the PCB layout may be contributing as well).  Every time one of the switches changes state a minute charge is injected into the signal path, which in it turn is combined into a small RF current synchronous with the LO.  Symmetry should cancel out most of it, but since the latter is not perfect a residual RF signal remains, which is furthermore phase shifted by the output impedance of the HF filters.  To make it short, several mVs of RF signal from the LO are present at the input of the QSD and are subsequently demodulated into DC.  I found the DC voltage levels consistent with a differential capacitance between the control and switch electrodes of ca. 0.1pF.  In the SDRtwo prototype saturation of one or both base band amplifiers occurred at specific range of frequencies above 22MHz.  In order to avoid this I added a DC cancellation feedback circuit on each instrumentation amplifier.  The circuit samples the output signal with an integrator with a long time constants, injecting a compensating DC voltage into the ground reference of the INA163.


Quadrature local oscillator

See part 2 for the circuit diagram.

The quadrature signal for the QSD is generated by the AD9854 chip, a quite complex animal from Analog Devices.  It contains, amongst many other modules that are not used in this application, a 48bit DDS engine, a sine look-up ROM table and a pair of 12bit ultra fast DACs.  The output of each DAC (differential current output) needs to be cleaned a bit (smoothing filter) by 7th order elliptic low pass filters at 35MHz, before they can be fed to a pair of comparators, providing the square signals of exact 50% duty cycle and exact 90° in phase needed for the QSD. 
Needless to say that the exactitude of the duty cycle and the phase relation is of paramount importance for a good working QSD.  Though the AD9854 in itself is fairly accurate, great care must be taken for the symmetry of the subsequent circuitry.

For the 7th order filter I found a elliptical filter design using constant inductor values.  I could lay my hand on some 1µH chip inductors, and scaled the this filter to 180Ohm impedance and a corner frequency of 35MHz.
Gerald Youngblood’s design the MAX9113 dual LVDS line receiver chip was used a squarer circuit, it yields an ultra low pulse skew according the data sheet, which is what is needed.

However, the circuit published in "A Software-Defined Radio for the Masses, part 4” does not work well.  The bias circuit for the positive inputs of the MAX9113 proposed herein (i.e. sampling the difference of the positive and negative current outputs of the DACs) yields some asymmetries that do not guarantee a 50% duty cycle of the square waves at the output, especially not at the higher frequencies. 
A remedy to that (as someone on the SDR-Radio Yahoo user group was so kind to point out) is to have a second set of identical filters feeding the positive inputs of the MAX9113.  With the rather elaborate setup of four identical 7th order filters, one for each DAC output, symmetry is fully restored, yielding the best possible conditions for the
exact 50% duty cycle and exact 90° in phase requirements.  The filters are built with regular accuracy components, the gain and phase characteristics of the individual filter is not so important as long as they are as much as possible similar between the filters. 
I understand that Flexradio’s SDR-1000 design has the same setup, though this has never been published (at least to my knowledge). 

The AD9854 is controlled using its serial mode. Since quite some pins needs nevertheless to be controlled, the parallel port of the PC was chosen to do so.  A 74LCV4245 performs the level shifting from the 5V logic (PC’s parallel port) to the 3.3V logic (inputs of the AD9854).  This may be somewhat overkill as the parallel port of my PC never gave anything more than 3.0V, but better be save than sorry, and I would not dare to connect a AD9854 directly to a connector. 
It appears further that this way of controlling the AD9854 (and thus the entire SDRtwo) is quite different from that of the Flexradio-1000 (simpler for that matter).  This is essentially due to the fact I didn’t have a description of this interface at the time of the design.

A crystal oscillator of 160MHz type HS-810 by NEL feeds the AD9854.  Although it was the only higher frequency oscillator module I could find, I would not recommend it for this design.  First: it has a single ELC compatible output, which led me to use the differential clock input feature of the AD9854 in an asymmetric way.  It works but it necessitates quite some extra resistors and capacitors.  Second: it dissipates a lot, taking some 80mA at 5V, with frequency drifts of several kHz during the warming up period as a consequence.
As it is suggested (the data sheet of the AD9854 is not too clear on this point) that the oscillator should be stopped during the reset sequence, I played it save and I implemented a PMOS switch in the power line.  This adds some extra safety, as the oscillator will stop (and the AD9854 will stop dissipating) when the data connection is disconnected.
The AD9854 runs on a 3.3V power supply and takes more than 200mA when clocked at 160MHz, even with the not used parts disabled.  As it heats quite a bit, a cute little dissipater was epoxied on top of the TQFP.


Power Supply & PC Interface

See part 3 for the circuit diagram.

This power circuit is straightforward: from a rather heavy battery adaptor of 9V at 350mA, the power is filtered and regulated by a +5V regulator (based on a 7805) and a +3.3V regulator (based on a LM317).  As the instrumentation amplifier work best in a dual supply set up, I used and an EPC1086P DC/DC converter module (I salvaged from an old Ethernet adapter board) to make –9V.  A 78L06 and 79L06 further regulates and filters the power voltages for the INA163s.
As in all direct conversion SDR receivers, there is a “bump” to be seen near the centre of the spectrum (ca. from –1kHz to +1kHz) when disconnecting the antenna.  This is due to the 1/f noise of the base band amplifiers, the purity of the LO, the residual hum of the power supply, etc.  It is not much worse than the “bump” of the Softrock-40 which has much less circuitry to make noise.

A 74HC164 8bit serial-in / parallel-out shift register is used in combination with a UNL2308 driver to drive the relays of the HF filter bands and gain setting.  No special arrangement was made to latch the bits as the serial programming is fast compared to the speed of the relays.

I abandoned the concept of a Galvanic isolation between the SDRtwo and the PC, as it was too cumbersome: 8 data lines and two audio lines.  Furthermore I feared that the audio isolation transformers would introduce extra gain and phase differentials on the I/Q signals.  It seems to work quite all right as such; I nevertheless included a ferrite toroid in both the data and audio connection.


Dialling application in Visual Basic

As I was not able to use PowerSDR (see further) and the other applications such as Rocky, M0KGK and SDR-Radio are actually meant for a fixed frequency receiver setup, I wrote a basic but workable GUI in Visual Basic 6.0 to control the frequency and gain of the SDRtwo, see the SDRtwo GUI
This small program features:
* a window for the frequency in Hz, including buttons for increasing/decreasing the frequency per digit,
* a window for a directory of stations,
* windows with the actual messages over the parallel port.

Those interested can download this program including its source here (zipped file).  Don’t forget to install “inpout32.dll” as the program uses it to access the parallel port.


Realisation and pictures

The SDRtwo is build in a nice Aluminium box measuring 168 * 103 * 56 mm (Conrad ref. 523232-02) fitting a set of three boards, assembled together they form more or less as a single Euro sized (160 * 100 mm) board.

The first board (double sided 100*130 mm) contains the HF filters, the QSD and base band amplifiers, it contains also the relay driver logic.  Mixed SMD and through hole technology was used on this board, as was dictated by the availability of the components.  Through hole components are mounted on the top of the board, SMD components on the bottom. The top (component side) is not etched and serves as ground plane, pins (or small lengths of wire) are simply being soldered on the top side for a ground connection.
The second board (single sided 100*30 mm) contains the power circuitry and the PC interface connector.  Only through hole components are used on this board.  As only the 8 data outputs of the parallel port are used, I used a 9 pin D-shell connector to connect to the PC interface.  I know this is odd, but I could not fit a 25 pin D-shell into the box.  A special cable connects the SDRtwo to the parallel port of the PC. 
The third board (double sided 30*100 mm) is in fact a small daughter board on top of the first board, it contains the AD9854 chip and associated circuitry, amongst other the smoothing filters.  Except for the crystal oscillator module and the PMOS switch, all components are SMD.  Mounting the AD9854 on the board represented quite a challenge indeed, since it comes in TQFP package (80 pins of a pitch of 0.65mm).  The bottom side is not etched and serves as ground plane. 

All boards were home made, see elsewhere on this Web site for some comments on the “manufacturing” process.
The schematics were drawn using the TinyCad freeware, the artwork was draw using the CirCad (free evaluation).  Find here a zipped file containing the drawings in their original format.

Find here the artwork drawings of the component/solder side (large zipped files in bmp format).   Note that these were the initial artwork drawings I used for the prototype.  The second set of smoothing filters at the DDS output and the DC cancellation circuitry was added later, as additional daughter boards.  If there is much interest (and I can spare the time) I promise to do an effort to update the drawings.

Testing was relatively straight forward, as most of the circuitry worked first time. I used a DMM, an RF counter combined with a logarithmic HF level meter (based on the famous AD8307 chip) calibrated in dBm (home build) and an old oscilloscope (dual, 10MHz, 20mV) as measuring instruments.  I also made used of an HP33290A wave generator I had in loan from a friend, it offers 0…15MHz, 20…5000mVeff output, modulatable in AM or FM.  Combined with two home build 50Ohm attenuators of respectively 20dB and 60dB, it proved to be an invaluable tool for my experiments, though admitted, it is a far cry from a real HF signal generator

Find here a few pictures of the current prototype:
* the HF, QSD and base band board top and bottom.
* the quadrature LO board top and bottom.
* the power board top and bottom.
* and the final assembly.  

The total cost of the SDRtwo turned around 150 euro, accounting for the components I had in already my junk box, the ones I could get as free samples and the ones I salvaged from discarded equipment. 


Tests and results so far

I am still performing tests on the prototype (when time permits).  Some comments already :
* a typical M0KGK-SDR screenshots (see further) of the 40m band maximum gain and minimum gain.  One can clearly see the digimode transmissions around 7040kHz and a few SSB transmissions around 7080kHz.

* a screenshot when injecting a -60dBm signal at 7040kHz, the image rejection is about 60dB here. The I vs. Q amplitude was 4% off, while the phase was 2° off, according to the M0KGK-SDR calibration screen.
* the noise floor when the antenna input is open.  When disconnecting the audio line the noise floor will decrease only by 5dB outside of the central "bump" area, while the "bump" itself will decrease by 30dB.
* the system gain of the SDRtwo is 39dB (antenna in Ţ audio out, measured at 7.06MHz) when set at its maximum gain. 
This represents 40db base band gain, and 6dB QSD intrinsic gain, minus 7dB losses in the HF filters and other imperfections. 
The minimum discernable signal (MSD) is around –120dBm (0.2µV), I had to extrapolate this figure a bit here as I have no means to inject a signal below –100dBm.

Direct conversion receivers are free of the birdies, at least in theory.  The SDRtwo is however plagued by a more disturbing phenomenon:  independent of the LO frequency a low level spike is observed travelling slowly forth and back (in ca. 20s) across the band processed by the SDR application (96kHz).  Knowing that there absolutely no other oscillating circuit in the SDRtwo than the 160MHz crystal module, one should exclude mixing products.  After a long while this phenomenon seems to disappear, this may be due to some warming up of the SRDtwo.  I have no clue whatsoever yet as to the cause of this.  The parasitic signal is only about 20dB above the noise floor, so it does not influence too much the reception of signals, still, I would be grateful for every hint.

I use two sound boards, one is the original SoundBlaster 16bit PCI plug in boards (PCI128, ancient already), the other is the SoundBlaster AudigySE PCI plug in board.  The latter is moderately priced and yields 96kS/s at 24bit with a dynamic range of nearly 100dB and a noise floor that is (almost) free from spikes.  As it is, both boards perform far better than the on board sound system that came with the mother board of my desk top PC (and which I disabled).  I used the RightMark Audio Analyzer 5.4 freeware to test their performance, caring especially for the total distortion, the intermodulation distortion and the dynamic range.
A word of care about the AudigySE, one should be sure that its original SoundBlasters drivers are installed, it will work without this drivers but when set at 96kS/s only the part from -24kHz to +24kHz of the band will show.
The AudigySE board is associated with SDR application and is permanently connected to the SDRtwo with its line-input connection.  Its line-out connection is connected to the line-in connection of the SoundBlaster 16bit PCI with a short cable.  The latter is actually the primary sound device of the PC and is connected to the speakers.  It is also used for the several demodulation/decoding application such as Hamscope, MultiPSK, Dream, etc. This setup works fine, though the setting of the several gains can be mind-boggling.

Finally, a word about the desktop PC: it is an (old and faithful) Athlon XP 1800+ running WinXP.  When running M0KGK-SDR together with Hamscope or MultiPSK it will load smoothly the CPU to almost 80% of its capacity.


The several SDR applications

As mentioned earlier there several SDR applications available as freeware on the Internet: PowerSDR, Rocky, M0KGK-SDR and SDRadio.  Save for PowerSDR I used all of them in conjunction with the SDRtwo.
What is required from a good SDR application besides the obvious filtering, demodulation, noise reduction and the lot, is a good set of (semi)-automatic features to compensate the imperfections of the hardware, such as:
* compensating the phase in function of the base band frequency (imperfections in the base band and ADC processing)
* compensating the gain in function of the base band frequency (imperfections in the base band and ADC processing)
* adjusting the phase in function of the LO frequency (asymmetries in the I/Q circuitry of the LO)
* swapping the I and Q signals (cabling conventions)
* delaying/advancing the Q signal by one sample (needed with some sound boards, e.g. with the Audigy SE.

To illustrate this, see hereafter the block diagram of a typical I/Q type SDR receiver, hardware and software.  The blocks in orange at the left represent the QSD front end hardware (the SDRtwo in this case), the blocks in grey at the right represent the “functional” parts of the SDR application, while the blocks in green in the centre represent the “non-functional” parts of the SDR application.  The latter form probably the greatest challenge to the application builder.

There are basically two ways to dial the frequency within an SDR application, both methods are quite equivalent, the choice depends on the available LO hardware:
* Dialling with the available hardware LO (e.g. DSS circuit) and having a fixed software IF frequency (and LO), e.g. something around 10…12kHz to avoid the noise and hum around the 0Hz. This is what is done in the PowerSDR application.
* Having a fixed (or stepped) hardware LO and dialling by moving the software LO around.  This is what is done in the other application.

Here follows a short discussion about the SDR applications:

PowerSDR: This one is open source (the only one so far) freeware made available by a community of programmers targeting Flexradio’s SDR-1000 hardware, together witch with it forms a multi band transceiver (SoftRock-40 is also supported). 
I very recently downloaded PowerSDR (version 1.6.2) and installed it along with Microsoft's .Net Framework.  It didn't not recognise my sound board, and I have still to understand how to calibrate the frequency, the level and the image rejection.
  So, no further comments as I didn’t use PowerSDR too much yet.
PowerSDR is written with Microsoft’s Visual Studio .Net in C++, C# and assembler.  I looked briefly into it, especially if I could adapt it to SDRtwo’s frequency control interface.  I was soon discouraged as it is huge and complex (700 plus source files representing more than 10Gbytes), moreover Visual Studio .Net has a steep learning curve (not to mention its costs). 

Rocky: Freeware made available by Alex Shovkoplyas (VE3NEA) targeting the SoftRock-40 hardware (and variants).  Very neat piece of software featuring a very good automatic I/Q balancing algorithm, see graph.  More than 50dB side band rejection can be achieved.
It has no provision for AM or FM reception, and as it is meant for a single frequency hardware it has no provision for adjusting the phase in function of the LO frequency, nor an API to set the centre frequency by an external program.

M0KGK-SDR: Freeware made available by Duncan Munro (M0KGK) also targeting the SoftRock-40 hardware (and variants).  It is my preferred SDR application.  Similar to Rocky in many respects though it goes quite a bit further: a more comprehensive GUI (a.o. to set the band pass filters), several post detection processing options and provisions for AM or FM reception.
Though it is also meant for a single frequency hardware (no provision for adjusting the phase in function of the LO frequency, or an API to set the centre frequency by an external program), it has at least a selector for several front ends (each with its own settings).
Good automatic I/Q balancing algorithm (3rd order interpolation to match the gain and the phase in function of the base band frequency), more than 50dB side band rejection can be achieved.

SDRadio: Freeware made available by Alberto di Bene (I2PHD) targeting many home builders, kind of an offspring of WinSDR which is very similar but meant for weak signal detection.  Rather unusual (but beautiful) GUI, featuring a very good AM and synchronous AM demodulator, as well as an FM demodulator.  No provision for an API to set the centre frequency by an external program (though it is rather easy to do it manually in the GUI). 
Worst is that it does not have an automatic I/Q balancing algorithm, only a single point manual setting that does not take the base band frequency into account, and (which is worse) has no possibility to delay/advance the Q signal by one sample (needed with the AudigySE sound board).

SDR applications are still quite new, versions are being released almost every month.  I expect that they will continue to evolve over the next months and years.  Reading the messages of the SDR related Yahoo groups (Win-Radio, SoftRock-40, …) gives a good feeling in which direction the technology is evolving, long before the publication of any articles. 
My personal whish list for added functionality includes:
* including a dialling part:  multiple LOs, station memory, flexible/programmable interface for the HW, …
* or alternatively, having an API for an external dialling application
* adjusting the phase/gain corrections in function of the LO frequency
* built in provisions to connect the digital output stream to Digimode decoding applications (similar to VAC),
* provisions for transmission, as SDR type exciters are becoming available.
As I realise that PowerSDR has probably all this functionality available already, and I should probably be courageous and search for a good programmers introduction to PowerSDR on the Internet.